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-rw-r--r--test/passes/expand-connect-indexed/bundle-vecs.fir13
1 files changed, 7 insertions, 6 deletions
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index c8235ade..7922c278 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -1,8 +1,8 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghi -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Expand Indexed Connects
circuit top :
- module q :
+ module top :
wire i : UInt
wire j : UInt
@@ -17,13 +17,14 @@ circuit top :
; CHECK: wire b$y : UInt<32>
; CHECK: b$x := a$0$x
; CHECK: node b$x#0 = i
- ; CHECK: when eq-uu(b$x#0, UInt(1)) :
+ ; CHECK: when eq(b$x#0, UInt(1)) :
; CHECK: b$x := a$1$x
- ; CHECK: a$0$y := b$y
; CHECK: node b$y#0 = i
- ; CHECK: when eq-uu(b$y#0, UInt(1)) :
+ ; CHECK: when eq(b$y#0, UInt(0)) :
+ ; CHECK: a$0$y := b$y
+ ; CHECK: when eq(b$y#0, UInt(1)) :
; CHECK: a$1$y := b$y
- j := b
+ j := b.x
; CHECK: Finished Expand Indexed Connects