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path: root/test/passes/expand-connect-indexed/bundle-vecs.fir
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-rw-r--r--test/passes/expand-connect-indexed/bundle-vecs.fir30
1 files changed, 15 insertions, 15 deletions
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index 901ab4e6..9d375087 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -7,23 +7,23 @@ circuit top :
wire j : UInt
wire a : { x : UInt<32>, flip y : UInt<32> }[2]
- ; CHECK: wire a_0_x : UInt<32>
- ; CHECK: wire a_0_y : UInt<32>
- ; CHECK: wire a_1_x : UInt<32>
- ; CHECK: wire a_1_y : UInt<32>
+ ; CHECK: wire a$0$x : UInt<32>
+ ; CHECK: wire a$0$y : UInt<32>
+ ; CHECK: wire a$1$x : UInt<32>
+ ; CHECK: wire a$1$y : UInt<32>
accessor b = a[i]
- ; CHECK: wire b_x : UInt<32>
- ; CHECK: wire b_y : UInt<32>
- ; CHECK: b_x := a_0_x
- ; CHECK: node b_x__0 = i
- ; CHECK: when eq(b_x__0, UInt(1)) :
- ; CHECK: b_x := a_1_x
- ; CHECK: node b_y__0 = i
- ; CHECK: when eq(b_y__0, UInt(0)) :
- ; CHECK: a_0_y := b_y
- ; CHECK: when eq(b_y__0, UInt(1)) :
- ; CHECK: a_1_y := b_y
+ ; CHECK: wire b$x : UInt<32>
+ ; CHECK: wire b$y : UInt<32>
+ ; CHECK: b$x := a$0$x
+ ; CHECK: node i#0 = i
+ ; CHECK: when eq(i#0, UInt(1)) :
+ ; CHECK: b$x := a$1$x
+ ; CHECK: node i#1 = i
+ ; CHECK: when eq(i#1, UInt(0)) :
+ ; CHECK: a$0$y := b$y
+ ; CHECK: when eq(i#1, UInt(1)) :
+ ; CHECK: a$1$y := b$y
j := b.x
; CHECK: Finished Expand Indexed Connects