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-rw-r--r--test/passes/expand-accessors/accessor-mem.fir12
-rw-r--r--test/passes/expand-accessors/accessor-vec.fir20
-rw-r--r--test/passes/expand-accessors/one-when.fir20
-rw-r--r--test/passes/expand-accessors/two-when.fir57
4 files changed, 20 insertions, 89 deletions
diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index 32002d47..01257279 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -5,15 +5,15 @@ circuit top :
module top :
mem m : UInt(32)[10][10][10]
wire i : UInt
- accessor a = m[i] ;CHECK: a := ReadPort(m, i, UInt(1))
- accessor b = a[i] ;CHECK: b := (a.9 a.8 a.7 a.6 a.5 a.4 a.3 a.2 a.1 a.0)[i]
- accessor c = b[i] ;CHECK: c := (b.9 b.8 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0)[i]
+ accessor a = m[i] ;CHECK: accessor a = m[i]
+ accessor b = a[i] ;CHECK: b := (a.0 a.1 a.2 a.3 a.4 a.5 a.6 a.7 a.8 a.9)[i]
+ accessor c = b[i] ;CHECK: c := (b.0 b.1 b.2 b.3 b.4 b.5 b.6 b.7 b.8 b.9)[i]
wire j : UInt
j := c
- accessor x = m[i] ;CHECK: WritePort(m, i, UInt(1)) := x
- accessor y = x[i] ;CHECK: (x.9 x.8 x.7 x.6 x.5 x.4 x.3 x.2 x.1 x.0)[i] := y
- accessor z = y[i] ;CHECK: (y.9 y.8 y.7 y.6 y.5 y.4 y.3 y.2 y.1 y.0)[i] := z
+ accessor x = m[i] ;CHECK: accessor x = m[i]
+ accessor y = x[i] ;CHECK: (x.0 x.1 x.2 x.3 x.4 x.5 x.6 x.7 x.8 x.9)[i] := y
+ accessor z = y[i] ;CHECK: (y.0 y.1 y.2 y.3 y.4 y.5 y.6 y.7 y.8 y.9)[i] := z
z := j
; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir
index 4314e062..599abb8f 100644
--- a/test/passes/expand-accessors/accessor-vec.fir
+++ b/test/passes/expand-accessors/accessor-vec.fir
@@ -5,15 +5,23 @@ circuit top :
module top :
wire m : UInt(32)[10][10][10]
wire i : UInt
- accessor a = m[i] ;CHECK: a := (m.9 m.8 m.7 m.6 m.5 m.4 m.3 m.2 m.1 m.0)[i]
- accessor b = a[i] ;CHECK: b := (a.9 a.8 a.7 a.6 a.5 a.4 a.3 a.2 a.1 a.0)[i]
- accessor c = b[i] ;CHECK: c := (b.9 b.8 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0)[i]
+ accessor a = m[i] ;CHECK: a := (m.0 m.1 m.2 m.3 m.4 m.5 m.6 m.7 m.8 m.9)[i]
+ accessor b = a[i] ;CHECK: b := (a.0 a.1 a.2 a.3 a.4 a.5 a.6 a.7 a.8 a.9)[i]
+ accessor c = b[i] ;CHECK: c := (b.0 b.1 b.2 b.3 b.4 b.5 b.6 b.7 b.8 b.9)[i]
wire j : UInt
j := c
- accessor x = m[i] ;CHECK: (m.9 m.8 m.7 m.6 m.5 m.4 m.3 m.2 m.1 m.0)[i] := x
- accessor y = x[i] ;CHECK: (x.9 x.8 x.7 x.6 x.5 x.4 x.3 x.2 x.1 x.0)[i] := y
- accessor z = y[i] ;CHECK: (y.9 y.8 y.7 y.6 y.5 y.4 y.3 y.2 y.1 y.0)[i] := z
+ accessor x = m[i] ;CHECK: (m.0 m.1 m.2 m.3 m.4 m.5 m.6 m.7 m.8 m.9)[i] := x
+ accessor y = x[i] ;CHECK: (x.0 x.1 x.2 x.3 x.4 x.5 x.6 x.7 x.8 x.9)[i] := y
+ accessor z = y[i] ;CHECK: (y.0 y.1 y.2 y.3 y.4 y.5 y.6 y.7 y.8 y.9)[i] := z
z := j
+ wire p : {n : UInt(32)[10]}
+ accessor q = p.n[i] ;CHECK: (p.n.0 p.n.1 p.n.2 p.n.3 p.n.4 p.n.5 p.n.6 p.n.7 p.n.8 p.n.9)[i] := q
+ q := j
+
+ wire r : {m : UInt(32)}[10]
+ accessor s = r[i] ;CHECK: s := (r.0 r.1 r.2 r.3 r.4 r.5 r.6 r.7 r.8 r.9)[i]
+ j := s.m
+
; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/one-when.fir b/test/passes/expand-accessors/one-when.fir
deleted file mode 100644
index 2597c1d7..00000000
--- a/test/passes/expand-accessors/one-when.fir
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s
-
-;CHECK: Expand Accessors
-circuit top :
- module top :
- mem m : UInt(1)[2]
- wire i : UInt(1)
- wire p : UInt(1)
- when p :
- accessor a = m[i] ;CHECK: a := ReadPort(m, i, bit-and(p, UInt(1)))
- i := a
- accessor b = m[i] ;CHECK: WritePort(m, i, bit-and(p, UInt(1))) := b
- b := i
- else :
- accessor c = m[i] ;CHECK: c := ReadPort(m, i, bit-and(equal-uu(UInt(0), p), UInt(1)))
- i := c
- accessor d = m[i] ;CHECK: WritePort(m, i, bit-and(equal-uu(UInt(0), p), UInt(1))) := d
- d := i
-
-; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/two-when.fir b/test/passes/expand-accessors/two-when.fir
deleted file mode 100644
index 87c8fc54..00000000
--- a/test/passes/expand-accessors/two-when.fir
+++ /dev/null
@@ -1,57 +0,0 @@
-; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s
-
-;CHECK: Expand Accessors
-circuit top :
- module top :
- mem m : UInt(1)[2]
- wire i : UInt(1)
- wire p : UInt(1)
- when p :
- wire p2 : UInt(1)
- when p2 :
- accessor a = m[i]
- i := a
- accessor b = m[i]
- b := i
- ;CHECK : wire a : UInt(1)
- ;CHECK : a := ReadPort(m, i, bit-and(p2, bit-and(p, UInt(1))))
- ;CHECK : i := a
- ;CHECK : wire b : UInt(1)
- ;CHECK : WritePort(m, i, bit-and(p2, bit-and(p, UInt(1)))) := b
- ;CHECK : b := i
- else :
- accessor c = m[i]
- i := c
- accessor d = m[i]
- d := i
- ;CHECK : wire c : UInt(1)
- ;CHECK : c := ReadPort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(p, UInt(1))))
- ;CHECK : i := c
- ;CHECK : wire d : UInt(1)
- ;CHECK : WritePort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(p, UInt(1)))) := d
- ;CHECK : d := i
- else :
- when p2 :
- accessor w = m[i]
- i := w
- accessor x = m[i]
- x := i
- ;CHECK : wire w : UInt(1)
- ;CHECK : w := ReadPort(m, i, bit-and(p2, bit-and(equal-uu(UInt(0), p), UInt(1))))
- ;CHECK : i := w
- ;CHECK : wire x : UInt(1)
- ;CHECK : WritePort(m, i, bit-and(p2, bit-and(equal-uu(UInt(0), p), UInt(1)))) := x
- ;CHECK : x := i
- else :
- accessor y = m[i]
- i := y
- accessor z = m[i]
- z := i
- ;CHECK : wire y : UInt(1)
- ;CHECK : y := ReadPort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(equal-uu(UInt(0), p), UInt(1))))
- ;CHECK : i := y
- ;CHECK : wire z : UInt(1)
- ;CHECK : WritePort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(equal-uu(UInt(0), p), UInt(1)))) := z
- ;CHECK : z := i
-
-; CHECK: Finished Expand Accessors
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-07 03:37:33 +0000