diff options
Diffstat (limited to 'test/parser')
| -rw-r--r-- | test/parser/bundle.fir | 26 | ||||
| -rw-r--r-- | test/parser/dshl.fir | 14 | ||||
| -rw-r--r-- | test/parser/gcd.fir | 2 | ||||
| -rw-r--r-- | test/parser/ints.fir | 20 | ||||
| -rw-r--r-- | test/parser/invalids.fir | 13 | ||||
| -rw-r--r-- | test/parser/mux.fir | 14 | ||||
| -rw-r--r-- | test/parser/node.fir | 16 |
7 files changed, 91 insertions, 14 deletions
diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir index dae02d2a..16a72a1b 100644 --- a/test/parser/bundle.fir +++ b/test/parser/bundle.fir @@ -24,21 +24,21 @@ circuit top : ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire z : { x : UInt, flip y : SInt} -; CHECK: z.x <= UInt("h1") -; CHECK: z.y <= SInt("h1") +; CHECK: z.x <= UInt<1>("h1") +; CHECK: z.y <= SInt<2>("h1") ; CHECK: node x = z.x ; CHECK: node y = z.y ; CHECK: wire a : UInt<3>[10] -; CHECK: a[0] <= UInt("h1") -; CHECK: a[1] <= UInt("h1") -; CHECK: a[2] <= UInt("h1") -; CHECK: a[3] <= UInt("h1") -; CHECK: a[4] <= UInt("h1") -; CHECK: a[5] <= UInt("h1") -; CHECK: a[6] <= UInt("h1") -; CHECK: a[7] <= UInt("h1") -; CHECK: a[8] <= UInt("h1") -; CHECK: a[9] <= UInt("h1") +; CHECK: a[0] <= UInt<1>("h1") +; CHECK: a[1] <= UInt<1>("h1") +; CHECK: a[2] <= UInt<1>("h1") +; CHECK: a[3] <= UInt<1>("h1") +; CHECK: a[4] <= UInt<1>("h1") +; CHECK: a[5] <= UInt<1>("h1") +; CHECK: a[6] <= UInt<1>("h1") +; CHECK: a[7] <= UInt<1>("h1") +; CHECK: a[8] <= UInt<1>("h1") +; CHECK: a[9] <= UInt<1>("h1") ; CHECK: node b = a[2] -; CHECK: node c = a[UInt("h3")] +; CHECK: node c = a[UInt<2>("h3")] diff --git a/test/parser/dshl.fir b/test/parser/dshl.fir new file mode 100644 index 00000000..99a6ec7d --- /dev/null +++ b/test/parser/dshl.fir @@ -0,0 +1,14 @@ +; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s +circuit GCD : + module GCD : + input a : UInt<63> + input b : UInt<63> + input sign : UInt<1> + output d : UInt + ;wire T_205 : UInt + node T_203 = UInt<6>("h3f") + node normCount = not(T_203) + node absIn = mux(sign, a, b) + node T_205 = dshl(absIn, normCount) + d <= T_205 + diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir index e0958a7a..45a048f2 100644 --- a/test/parser/gcd.fir +++ b/test/parser/gcd.fir @@ -4,7 +4,7 @@ circuit GCD : input e : UInt<1> input clk : Clock input reset : UInt<1> - output z : UInt<16> + output z : UInt output v : UInt<1> input a : UInt<16> input b : UInt<16> diff --git a/test/parser/ints.fir b/test/parser/ints.fir new file mode 100644 index 00000000..0c79276b --- /dev/null +++ b/test/parser/ints.fir @@ -0,0 +1,20 @@ +; RUN: firrtl -i %s -o %s.out -X firrtl 2>&1 | tee %s.out | FileCheck %s +: XFAIL: * + +circuit top : + module top : + output a : UInt + output b : SInt + output c : SInt + a <= UInt(8) + b <= SInt(8) + c <= SInt(-8) + +; CHECK: circuit top : +; CHECK: module top : +; CHECK: output a : UInt +; CHECK: output b : SInt +; CHECK: output c : SInt +; CHECK: a <= UInt<4>("h8") +; CHECK: b <= SInt<5>("h08") +; CHECK: c <= SInt<4>("h8") diff --git a/test/parser/invalids.fir b/test/parser/invalids.fir new file mode 100644 index 00000000..65051832 --- /dev/null +++ b/test/parser/invalids.fir @@ -0,0 +1,13 @@ +; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s +; CHECK: Done! +circuit GCD : + module GCD : + input x : UInt<128> + input p : UInt<1> + input q : UInt<1> + input clk : Clock + wire w : UInt[3] + w is invalid + w[0] <= UInt(0) + w[1] <= UInt(0) + w[2] <= UInt(0) diff --git a/test/parser/mux.fir b/test/parser/mux.fir new file mode 100644 index 00000000..4705aa75 --- /dev/null +++ b/test/parser/mux.fir @@ -0,0 +1,14 @@ +; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s +circuit GCD : + module GCD : + input e : UInt<1> + input f : UInt<1> + input g : UInt<1> + output o : UInt<1> + node y = f + node z = f + node x = mux(UInt<1>(0),y,z) + o <= x + + + diff --git a/test/parser/node.fir b/test/parser/node.fir new file mode 100644 index 00000000..193aed88 --- /dev/null +++ b/test/parser/node.fir @@ -0,0 +1,16 @@ +; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s +; CHECK: Done! +circuit GCD : + module GCD : + input x : UInt<128> + input p : UInt<1> + input q : UInt<1> + input clk : Clock + reg addr : UInt, clk with : + reset => (UInt<1>("h0"), addr) + when p : + node T_1234 = bits(x, 63, 24) + addr <= T_1234 + when q : + node T_1380 = tail(x, 1) + addr <= T_1380 |