3 files changed, 47 insertions, 0 deletions
diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir
new file mode 100644
index 00000000..30c59fb9
--- /dev/null
+++ b/test/features/InitializeVec.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+circuit Tst : 
+  module Tst : 
+    output in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}
+    output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4]
+    
+    in.ready := UInt<1>(1)
+    outs[0].valid := UInt<1>(0)
+    outs[0].bits := UInt<1>(0)
+    outs[1].valid := UInt<1>(0)
+    outs[1].bits := UInt<1>(0)
+    outs[2].valid := UInt<1>(0)
+    outs[2].bits := UInt<1>(0)
+    outs[3].valid := UInt<1>(0)
+    outs[3].bits := UInt<1>(0)
+    in.ready := UInt<1>(1)
+    infer accessor out = outs[in.bits]
+    when out.ready : 
+      out.bits := UInt<7>(99)
+      out.valid := UInt<1>(1)
diff --git a/test/features/Link.fir b/test/features/Link.fir
new file mode 100644
index 00000000..190341f2
--- /dev/null
+++ b/test/features/Link.fir
@@ -0,0 +1,14 @@
+; RUN: firrtl -i %s -m /Users/cusgadmin/code/stanza/firrtl/test/features/Queue.fir -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+;CHECK: Lower To Ground
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    input reset : UInt<1>
+    output out : UInt<10>
+    
+    inst q of Queue
+    q.clk := clk
+    q.reset := reset
+    q.in := UInt(1)
+    out := q.out
+
diff --git a/test/features/Queue.fir b/test/features/Queue.fir
new file mode 100644
index 00000000..345d2a44
--- /dev/null
+++ b/test/features/Queue.fir
@@ -0,0 +1,12 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit Queue :
+  module Queue :
+    input in : UInt<10>
+    output out : UInt<10>
+    input clk : Clock
+    input reset : UInt<1>
+  
+    reg r : UInt<10>,clk,reset
+    r := in
+    out := r