1 files changed, 0 insertions, 18 deletions
diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir
deleted file mode 100644
index 96022933..00000000
--- a/test/features/VerilogReg.fir
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Done!
-circuit Poison :
-  module Poison :
-    input clk : Clock
-    input reset : UInt<1>
-    input p1 : UInt<1>
-    input p2 : UInt<1>
-    input p3 : UInt<1>
-    reg r : UInt<32>,clk with :
-       reset => (reset,r)
-    when p1 :
-       r <= UInt(1)
-    when p2 :
-       r <= UInt(2)
-    when p3 :
-       r <= UInt(3)
-