diff options
Diffstat (limited to 'test/features/VerilogReg.fir')
| -rw-r--r-- | test/features/VerilogReg.fir | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir index 33c4417f..96022933 100644 --- a/test/features/VerilogReg.fir +++ b/test/features/VerilogReg.fir @@ -7,7 +7,8 @@ circuit Poison : input p1 : UInt<1> input p2 : UInt<1> input p3 : UInt<1> - reg r : UInt<32>,clk,reset,r + reg r : UInt<32>,clk with : + reset => (reset,r) when p1 : r <= UInt(1) when p2 : |