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-rw-r--r--test/features/IsInvalid.fir5
1 files changed, 3 insertions, 2 deletions
diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir
index cf898fe9..f6766bf2 100644
--- a/test/features/IsInvalid.fir
+++ b/test/features/IsInvalid.fir
@@ -12,9 +12,10 @@ circuit Top :
write-latency => 1
reader => r
writer => w
- read-writer => rw
+ readwriter => rw
wire x : { w : UInt<42>, x : UInt<20>}
- reg c : { w : UInt<42>, x : UInt<20>},clk,reset,x
+ reg c : { w : UInt<42>, x : UInt<20>},clk with :
+ reset => (reset,x)
inst other of Other
clk is invalid