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-rw-r--r--test/errors/high-form/InvalidLOC.fir4
1 files changed, 1 insertions, 3 deletions
diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir
index 5270577b..cbbb53a9 100644
--- a/test/errors/high-form/InvalidLOC.fir
+++ b/test/errors/high-form/InvalidLOC.fir
@@ -1,5 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
@@ -10,7 +9,6 @@ circuit Top :
module Top :
wire x : UInt
add(x,x) := UInt(1)
- Pad(x,?) := UInt(1)
Register(x,x) := UInt(1)
ReadPort(x,x,x) := UInt(1)
UInt(1) := UInt(1)