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Diffstat (limited to 'test/errors/gender/BulkWrong.fir')
| -rw-r--r-- | test/errors/gender/BulkWrong.fir | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir new file mode 100644 index 00000000..2b1792aa --- /dev/null +++ b/test/errors/gender/BulkWrong.fir @@ -0,0 +1,12 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; CHECK: Expression req is used as a sink but can only be used as a source. + +circuit BTB : + module BTB : + input clk : Clock + input reset : UInt<1> + input req : {valid : UInt<1>, bits : {addr : UInt<39>}} + + wire x : {valid : UInt<1>, bits : {addr : UInt<39>}} + + req <> x |