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-rw-r--r--test/chisel3/Tbl.fir4
1 files changed, 2 insertions, 2 deletions
diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir
index e7397f61..013fd098 100644
--- a/test/chisel3/Tbl.fir
+++ b/test/chisel3/Tbl.fir
@@ -11,9 +11,9 @@ circuit Tbl :
cmem m : UInt<10>[256]
o := UInt<1>(0)
when we :
- accessor T_13 = m[i]
+ infer accessor T_13 = m[i]
node T_14 = bits(d, 9, 0)
T_13 := T_14
else :
- accessor T_15 = m[i]
+ infer accessor T_15 = m[i]
o := T_15