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-rw-r--r--test/chisel3/Mul.fir2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index c5dccb6f..b80b8a83 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -26,5 +26,5 @@ circuit Mul :
tbl[15] := UInt<4>(9)
node T_42 = shl(x, 2)
node T_43 = bit-or(T_42, y)
- accessor T_44 = tbl[T_43]
+ infer accessor T_44 = tbl[T_43]
z := T_44