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Diffstat (limited to 'test/chisel3/LFSR16.fir')
| -rw-r--r-- | test/chisel3/LFSR16.fir | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir deleted file mode 100644 index 29a2823a..00000000 --- a/test/chisel3/LFSR16.fir +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s -;CHECK: Done! - -circuit LFSR16 : - module LFSR16 : - output out : UInt<16> - input inc : UInt<1> - - reg res : UInt<16> - on-reset res := UInt<16>(1) - when inc : - node T_16 = bit(res, 0) - node T_17 = bit(res, 2) - node T_18 = bit-xor(T_16, T_17) - node T_19 = bit(res, 3) - node T_20 = bit-xor(T_18, T_19) - node T_21 = bit(res, 5) - node T_22 = bit-xor(T_20, T_21) - node T_23 = bits(res, 15, 1) - node T_24 = cat(T_22, T_23) - res := T_24 - out := res |