3 files changed, 75 insertions, 7 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
index 03fd5ffa..af6761fd 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
@@ -18,9 +18,14 @@ import wiring._
   */
 object PinAnnotation {
   def apply(target: CircuitName, pins: Seq[String]): Annotation = {
-    Annotation(target, classOf[ReplaceMemMacros], pins.foldLeft("") { (str, p) => str + "pin:" + p + " " } )
+    Annotation(target, classOf[ReplaceMemMacros], s"pins:${pins.mkString(" ")}")
+  }
+  private val matcher = "pins:(.*)".r
+  def unapply(a: Annotation): Option[(CircuitName, Seq[String])] = a match {
+    case Annotation(CircuitName(c), _, matcher(rest)) =>
+      Some((CircuitName(c), rest.split(" ")))
+    case _ => None
   }
-  val matcher = "pin:([^ ]+)".r
 }
 
 /** Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file.
@@ -219,11 +224,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform {
     writer.serialize()
     val pins = getMyAnnotations(state) match {
       case Nil => Nil
-      case Seq(Annotation(c, t, string)) =>
-        PinAnnotation.matcher.findAllIn(string).toSeq match {
-          case Nil => error(s"Bad Annotation: ${Annotation(c, t, string)}")
-          case seq => seq
-        }
+      case Seq(PinAnnotation(CircuitName(c), pins)) => pins
       case _ => throwInternalError
     }
     val annos = pins.foldLeft(Seq[Annotation]()) { (seq, pin) =>
diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala
index 9069c145..2ac45e0b 100644
--- a/src/test/scala/firrtlTests/ClockListTests.scala
+++ b/src/test/scala/firrtlTests/ClockListTests.scala
@@ -115,4 +115,37 @@ class ClockListTests extends FirrtlFlatSpec {
     val retC = new ClockList("A", writer).run(c)
     (writer.toString) should be (check)
   }
+  "Have not circuit main be top of clocklist pass" should "still work" in {
+    val input =
+      """circuit A :
+        |  module A :
+        |    input clock: Clock
+        |    input clkB: Clock
+        |    inst b of B
+        |    inst d of D
+        |    b.clock <= clkB
+        |    b.clkC <= clock
+        |  module B :
+        |    input clock: Clock
+        |    input clkC: Clock
+        |    inst c of C
+        |    c.clock <= clkC
+        |  module C :
+        |    input clock: Clock
+        |    reg r: UInt<5>, clock
+        |  extmodule D :
+        |    input clock: Clock
+        |""".stripMargin
+    val check =
+  """Sourcelist: List(clock, clkC)
+    |Good Origin of clock is clock
+    |Good Origin of c.clock is clkC
+    |""".stripMargin
+    val c = passes.foldLeft(parse(input)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+    val writer = new StringWriter()
+    val retC = new ClockList("B", writer).run(c)
+    (writer.toString) should be (check)
+  }
 }
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index e84cbf47..01ad573f 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -345,4 +345,38 @@ class WiringTests extends FirrtlFlatSpec {
     val retC = wiringPass.run(c)
     (parse(retC.serialize).serialize) should be (parse(check).serialize)
   }
+
+  "Wiring annotations" should "work" in {
+    val source = SourceAnnotation(ComponentName("r", ModuleName("Top", CircuitName("Top"))), "pin")
+    val sink = SinkAnnotation(ModuleName("X", CircuitName("Top")), "pin")
+    val top = TopAnnotation(ModuleName("Top", CircuitName("Top")), "pin")
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    inst x of X
+        |    reg r: UInt<5>, clk
+        |  extmodule X :
+        |    input clk: Clock
+        |""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    inst x of X
+        |    reg r: UInt<5>, clk
+        |    wire r_0 : UInt<5>
+        |    r_0 <= r
+        |    x.pin <= r_0
+        |  extmodule X :
+        |    input clk: Clock
+        |    input pin: UInt<5>
+        |""".stripMargin
+    val c = passes.foldLeft(parse(input)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+    val wiringXForm = new WiringTransform()
+    val retC = wiringXForm.execute(CircuitState(c, LowForm, Some(AnnotationMap(Seq(source, sink, top))), None)).circuit
+    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+  }
 }