1 files changed, 39 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
index 9ccff256..9b1f3a9c 100644
--- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala
+++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
@@ -24,7 +24,9 @@ class CheckInitializationSpec extends FirrtlFlatSpec {
      ExpandConnects,
      RemoveAccesses,
      ExpandWhens,
-     CheckInitialization)
+     CheckInitialization,
+     InferTypes
+  )
   "Missing assignment in consequence branch" should "trigger a PassException" in {
     val input =
       """circuit Test :
@@ -54,6 +56,42 @@ class CheckInitializationSpec extends FirrtlFlatSpec {
       }
     }
   }
+
+  "Assign after incomplete assignment" should "work" in {
+    val input =
+      """circuit Test :
+        |  module Test :
+        |    input p : UInt<1>
+        |    wire x : UInt<32>
+        |    when p :
+        |      x <= UInt(1)
+        |    x <= UInt(1)
+        |    """.stripMargin
+    passes.foldLeft(CircuitState(parse(input), UnknownForm)) {
+      (c: CircuitState, p: Transform) => p.runTransform(c)
+    }
+  }
+
+  "Assign after nested incomplete assignment" should "work" in {
+    val input =
+      """circuit Test :
+        |  module Test :
+        |    input p : UInt<1>
+        |    input q : UInt<1>
+        |    wire x : UInt<32>
+        |    when p :
+        |      when q :
+        |        x is invalid
+        |    else :
+        |      when q :
+        |        x <= UInt(2)
+        |    x <= UInt(1)
+        |    """.stripMargin
+    passes.foldLeft(CircuitState(parse(input), UnknownForm)) {
+      (c: CircuitState, p: Transform) => p.runTransform(c)
+    }
+  }
+
   "Missing assignment to submodule port" should "trigger a PassException" in {
     val input =
       """circuit Test :