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-rw-r--r--src/test/scala/firrtlTests/CheckSpec.scala44
-rw-r--r--src/test/scala/firrtlTests/InlineInstancesTests.scala54
-rw-r--r--src/test/scala/firrtlTests/LowerTypesSpec.scala19
-rw-r--r--src/test/scala/firrtlTests/ParserSpec.scala21
-rw-r--r--src/test/scala/firrtlTests/VerilogEquivalenceSpec.scala160
5 files changed, 218 insertions, 80 deletions
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 1137f8cd..a3efc784 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -384,6 +384,36 @@ class CheckSpec extends AnyFlatSpec with Matchers {
}
}
+ "Attempting to shadow a statement name" should "throw an error" in {
+ val input =
+ s"""|circuit scopes:
+ | module scopes:
+ | input c: Clock
+ | input i: UInt<1>
+ | output o: UInt<1>
+ | wire x: UInt<1>
+ | when i:
+ | stop(c, UInt(1), 1) : x
+ | o <= and(x, i)
+ |""".stripMargin
+ assertThrows[CheckHighForm.NotUniqueException] {
+ checkHighInput(input)
+ }
+ }
+
+ "Colliding statement names" should "throw an error" in {
+ val input =
+ s"""|circuit test:
+ | module test:
+ | input c: Clock
+ | stop(c, UInt(1), 1) : x
+ | stop(c, UInt(1), 1) : x
+ |""".stripMargin
+ assertThrows[CheckHighForm.NotUniqueException] {
+ checkHighInput(input)
+ }
+ }
+
"Conditionally statements" should "create separate consequent and alternate scopes" in {
val input =
s"""|circuit scopes:
@@ -536,6 +566,20 @@ class CheckSpec extends AnyFlatSpec with Matchers {
}
}
+ it should "throw an exception if a statement name is used as a reference" in {
+ val src = """
+ |circuit test:
+ | module test:
+ | input clock: Clock
+ | output a: UInt<2>
+ | stop(clock, UInt(1), 1) : hello
+ | a <= hello
+ |""".stripMargin
+ assertThrows[CheckHighForm.UndeclaredReferenceException] {
+ checkHighInput(src)
+ }
+ }
+
}
object CheckSpec {
diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala
index 6bee2b77..cc7257d2 100644
--- a/src/test/scala/firrtlTests/InlineInstancesTests.scala
+++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala
@@ -460,6 +460,60 @@ class InlineInstancesTests extends LowTransformSpec {
)
}
+ "inlining named statements" should "work" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | input clock : Clock
+ | input a : UInt<32>
+ | output b : UInt<32>
+ | inst i of Inline
+ | i.clock <= clock
+ | i.a <= a
+ | b <= i.b
+ | module Inline :
+ | input clock : Clock
+ | input a : UInt<32>
+ | output b : UInt<32>
+ | b <= a
+ | assert(clock, UInt(1), eq(a,b), "a == b") : assert1
+ | assert(clock, UInt(1), not(eq(a,b)), "a != b")
+ | stop(clock, UInt(0), 0)
+ |""".stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | input clock : Clock
+ | input a : UInt<32>
+ | output b : UInt<32>
+ | wire i_clock : Clock
+ | wire i_a : UInt<32>
+ | wire i_b : UInt<32>
+ | i_b <= i_a
+ | assert(i_clock, UInt(1), eq(i_a, i_b), "a == b") : i_assert1
+ | assert(i_clock, UInt(1), not(eq(i_a, i_b)), "a != b")
+ | stop(i_clock, UInt(0), 0)
+ | b <= i_b
+ | i_clock <= clock
+ | i_a <= a
+ |""".stripMargin
+ val top = CircuitTarget("Top").module("Top")
+ val inlined = top.instOf("i", "Inline")
+
+ executeWithAnnos(
+ input,
+ check,
+ Seq(
+ inline("Inline"),
+ NoCircuitDedupAnnotation,
+ DummyAnno(inlined.ref("assert1"))
+ ),
+ Seq(
+ DummyAnno(top.ref("i_assert1"))
+ )
+ )
+ }
+
"inlining both grandparent and grandchild" should "should work" in {
val input =
"""circuit Top :
diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala
index da84b362..78d03e68 100644
--- a/src/test/scala/firrtlTests/LowerTypesSpec.scala
+++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala
@@ -321,6 +321,25 @@ class LowerTypesUniquifySpec extends FirrtlFlatSpec {
executeTest(input, expected)
}
+ it should "rename nodes colliding with labled statements" in {
+ val input =
+ """circuit Test :
+ | module Test :
+ | input clock : Clock
+ | reg x : { b : UInt<1>, c : { d : UInt<2>, e : UInt<3>}[2], c_1_e : UInt<4>}[2], clock
+ | node a = x
+ | printf(clock, UInt(1), "") : a_0_c_
+ | assert(clock, UInt(1), UInt(1), "") : a__0
+ """.stripMargin
+ val expected = Seq(
+ "node a___0_b = x_0_b",
+ "node a___1_c__1_e = x_1_c__1_e",
+ "node a___1_c_1_e = x_1_c_1_e"
+ )
+
+ executeTest(input, expected)
+ }
+
it should "rename DefRegister expressions: clock, reset, and init" in {
val input =
"""circuit Test :
diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala
index 373b960c..ba61b134 100644
--- a/src/test/scala/firrtlTests/ParserSpec.scala
+++ b/src/test/scala/firrtlTests/ParserSpec.scala
@@ -147,6 +147,27 @@ class ParserSpec extends FirrtlFlatSpec {
}
}
+ // ********** Statement labels **********
+ it should "allow certain statement to have a label" in {
+ val prelude = Seq("circuit top :", " module top :", " input c : Clock")
+ val statements = Seq("stop(c, UInt(1), 0)", "printf(c, UInt(1), \"\")") ++
+ Seq("assert", "assume", "cover").map(_ + "(c, UInt(1), UInt(1), \"\")")
+ val validLabels = Seq(":test" -> "test", " :test" -> "test", " : test" -> "test", " : test01" -> "test01")
+ statements.foreach { stmt =>
+ validLabels.foreach {
+ case (lbl, expected) =>
+ val line = " " + stmt + lbl
+ val src = (prelude :+ line).mkString("\n") + "\n"
+ val res = firrtl.Parser.parse(src)
+ CircuitState(res, Nil) should containTree {
+ case s: Stop => s.name == expected
+ case s: Print => s.name == expected
+ case s: Verification => s.name == expected
+ }
+ }
+ }
+ }
+
// ********** Keywords **********
"Keywords" should "be allowed as Ids" in {
import KeywordTests._
diff --git a/src/test/scala/firrtlTests/VerilogEquivalenceSpec.scala b/src/test/scala/firrtlTests/VerilogEquivalenceSpec.scala
index d88309ce..747f6689 100644
--- a/src/test/scala/firrtlTests/VerilogEquivalenceSpec.scala
+++ b/src/test/scala/firrtlTests/VerilogEquivalenceSpec.scala
@@ -7,116 +7,116 @@ import firrtl.testutils._
class VerilogEquivalenceSpec extends FirrtlFlatSpec {
"mul followed by cat" should "be correct" in {
val header = s"""
- |circuit Multiply :
- | module Multiply :
- | input x : UInt<4>
- | input y : UInt<2>
- | input z : UInt<2>
- | output out : UInt<8>
- |""".stripMargin
+ |circuit Multiply :
+ | module Multiply :
+ | input x : UInt<4>
+ | input y : UInt<2>
+ | input z : UInt<2>
+ | output out : UInt<8>
+ |""".stripMargin
val input1 = header + """
- | out <= cat(z, mul(x, y))""".stripMargin
+ | out <= cat(z, mul(x, y))""".stripMargin
val input2 = header + """
- | node n = mul(x, y)
- | node m = cat(z, n)
- | out <= m""".stripMargin
+ | node n = mul(x, y)
+ | node m = cat(z, n)
+ | out <= m""".stripMargin
val expected = s"""
- |module MultiplyRef(
- | input [3:0] x,
- | input [1:0] y,
- | input [1:0] z,
- | output [7:0] out
- |);
- | wire [5:0] w = x * y;
- | assign out = {z, w};
- |endmodule""".stripMargin
+ |module MultiplyRef(
+ | input [3:0] x,
+ | input [1:0] y,
+ | input [1:0] z,
+ | output [7:0] out
+ |);
+ | wire [5:0] w = x * y;
+ | assign out = {z, w};
+ |endmodule""".stripMargin
firrtlEquivalenceWithVerilog(input1, expected)
firrtlEquivalenceWithVerilog(input2, expected)
}
"div followed by cat" should "be correct" in {
val header = s"""
- |circuit Divide :
- | module Divide :
- | input x : UInt<4>
- | input y : UInt<2>
- | input z : UInt<2>
- | output out : UInt<6>
- |""".stripMargin
+ |circuit Divide :
+ | module Divide :
+ | input x : UInt<4>
+ | input y : UInt<2>
+ | input z : UInt<2>
+ | output out : UInt<6>
+ |""".stripMargin
val input1 = header + """
- | out <= cat(z, div(x, y))""".stripMargin
+ | out <= cat(z, div(x, y))""".stripMargin
val input2 = header + """
- | node n = div(x, y)
- | node m = cat(z, n)
- | out <= m""".stripMargin
+ | node n = div(x, y)
+ | node m = cat(z, n)
+ | out <= m""".stripMargin
val expected = s"""
- |module DivideRef(
- | input [3:0] x,
- | input [1:0] y,
- | input [1:0] z,
- | output [5:0] out
- |);
- | wire [3:0] w = x / y;
- | assign out = {z, w};
- |endmodule""".stripMargin
+ |module DivideRef(
+ | input [3:0] x,
+ | input [1:0] y,
+ | input [1:0] z,
+ | output [5:0] out
+ |);
+ | wire [3:0] w = x / y;
+ | assign out = {z, w};
+ |endmodule""".stripMargin
firrtlEquivalenceWithVerilog(input1, expected)
firrtlEquivalenceWithVerilog(input2, expected)
}
"signed mul followed by cat" should "be correct" in {
val header = s"""
- |circuit SignedMultiply :
- | module SignedMultiply :
- | input x : SInt<4>
- | input y : SInt<2>
- | input z : SInt<2>
- | output out : UInt<8>
- |""".stripMargin
+ |circuit SignedMultiply :
+ | module SignedMultiply :
+ | input x : SInt<4>
+ | input y : SInt<2>
+ | input z : SInt<2>
+ | output out : UInt<8>
+ |""".stripMargin
val input1 = header + """
- | out <= cat(z, mul(x, y))""".stripMargin
+ | out <= cat(z, mul(x, y))""".stripMargin
val input2 = header + """
- | node n = mul(x, y)
- | node m = cat(z, n)
- | out <= m""".stripMargin
+ | node n = mul(x, y)
+ | node m = cat(z, n)
+ | out <= m""".stripMargin
val expected = s"""
- |module SignedMultiplyRef(
- | input signed [3:0] x,
- | input signed [1:0] y,
- | input signed [1:0] z,
- | output [7:0] out
- |);
- | wire [5:0] w = x * y;
- | assign out = {z, w};
- |endmodule""".stripMargin
+ |module SignedMultiplyRef(
+ | input signed [3:0] x,
+ | input signed [1:0] y,
+ | input signed [1:0] z,
+ | output [7:0] out
+ |);
+ | wire [5:0] w = x * y;
+ | assign out = {z, w};
+ |endmodule""".stripMargin
firrtlEquivalenceWithVerilog(input1, expected)
firrtlEquivalenceWithVerilog(input2, expected)
}
"signed div followed by cat" should "be correct" in {
val header = s"""
- |circuit SignedDivide :
- | module SignedDivide :
- | input x : SInt<4>
- | input y : SInt<2>
- | input z : SInt<2>
- | output out : UInt<7>
- |""".stripMargin
+ |circuit SignedDivide :
+ | module SignedDivide :
+ | input x : SInt<4>
+ | input y : SInt<2>
+ | input z : SInt<2>
+ | output out : UInt<7>
+ |""".stripMargin
val input1 = header + """
- | out <= cat(z, div(x, y))""".stripMargin
+ | out <= cat(z, div(x, y))""".stripMargin
val input2 = header + """
- | node n = div(x, y)
- | node m = cat(z, n)
- | out <= m""".stripMargin
+ | node n = div(x, y)
+ | node m = cat(z, n)
+ | out <= m""".stripMargin
val expected = s"""
- |module SignedDivideRef(
- | input signed [3:0] x,
- | input signed [1:0] y,
- | input signed [1:0] z,
- | output [6:0] out
- |);
- | wire [4:0] w = x / y;
- | assign out = {z, w};
- |endmodule""".stripMargin
+ |module SignedDivideRef(
+ | input signed [3:0] x,
+ | input signed [1:0] y,
+ | input signed [1:0] z,
+ | output [6:0] out
+ |);
+ | wire [4:0] w = x / y;
+ | assign out = {z, w};
+ |endmodule""".stripMargin
firrtlEquivalenceWithVerilog(input1, expected)
firrtlEquivalenceWithVerilog(input2, expected)
}
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 15:44:12 +0000