2 files changed, 1 insertions, 10 deletions
diff --git a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
index 88095830..72b006ec 100644
--- a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
@@ -3,12 +3,9 @@
 package firrtlTests.transforms
 
 import firrtlTests.FirrtlFlatSpec
-import org.scalatest._
-import org.scalatest.prop._
 import firrtl._
 import firrtl.passes._
 import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation}
-import firrtl.ir.Circuit
 import firrtl.annotations._
 import firrtl.annotations.TargetToken.{Field, Index}
 
diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
index 1c01d6d2..089f4a10 100644
--- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
+++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
@@ -3,21 +3,15 @@
 package firrtlTests
 package transforms
 
-import org.scalatest.FlatSpec
-import org.scalatest.Matchers
-import org.scalatest.junit.JUnitRunner
 import java.io._
 
 import firrtl._
-import firrtl.ir.{Circuit, Type, GroundType, IntWidth}
+import firrtl.ir.{Type, GroundType, IntWidth}
 import firrtl.Parser
-import firrtl.passes.PassExceptions
 import firrtl.annotations.{
-   Named,
    CircuitName,
    ModuleName,
    ComponentName,
-   Annotation,
    Target
 }
 import firrtl.transforms.TopWiring._