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-rw-r--r--src/test/scala/firrtlTests/transforms/DedupTests.scala243
1 files changed, 233 insertions, 10 deletions
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index b66f7f9d..5ee2b927 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -3,14 +3,24 @@
package firrtlTests
package transforms
+import firrtl.RenameMap
import firrtl.annotations._
-import firrtl.transforms.{DedupModules}
+import firrtl.transforms.DedupModules
/**
* Tests inline instances transformation
*/
class DedupModuleTests extends HighTransformSpec {
+ case class MultiTargetDummyAnnotation(targets: Seq[Target], tag: Int) extends Annotation {
+ override def update(renames: RenameMap): Seq[Annotation] = {
+ val newTargets = targets.flatMap(renames(_))
+ Seq(MultiTargetDummyAnnotation(newTargets, tag))
+ }
+ }
+ case class SingleTargetDummyAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] {
+ override def duplicate(n: ComponentName): Annotation = SingleTargetDummyAnnotation(n)
+ }
def transform = new DedupModules
"The module A" should "be deduped" in {
val input =
@@ -135,7 +145,7 @@ class DedupModuleTests extends HighTransformSpec {
""".stripMargin
execute(input, check, Seq(dontDedup("A")))
}
- "The module A and A_" should "be deduped even with different port names and info, and annotations should remap" in {
+ "The module A and A_" should "be deduped even with different port names and info, and annotations should remapped" in {
val input =
"""circuit Top :
| module Top :
@@ -161,16 +171,12 @@ class DedupModuleTests extends HighTransformSpec {
| output x: UInt<1> @[yy 2:2]
| x <= UInt(1)
""".stripMargin
- case class DummyAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] {
- override def duplicate(n: ComponentName): Annotation = DummyAnnotation(n)
- }
val mname = ModuleName("Top", CircuitName("Top"))
- val finalState = execute(input, check, Seq(DummyAnnotation(ComponentName("a2.y", mname))))
-
- finalState.annotations.collect({ case d: DummyAnnotation => d }).head should be(DummyAnnotation(ComponentName("a2.x", mname)))
-
+ val finalState = execute(input, check, Seq(SingleTargetDummyAnnotation(ComponentName("a2.y", mname))))
+ finalState.annotations.collect({ case d: SingleTargetDummyAnnotation => d }).head should be(SingleTargetDummyAnnotation(ComponentName("a2.x", mname)))
}
+
"Extmodules" should "with the same defname and parameters should dedup" in {
val input =
"""circuit Top :
@@ -215,6 +221,7 @@ class DedupModuleTests extends HighTransformSpec {
execute(input, check, Seq.empty)
}
+
"Extmodules" should "with the different defname or parameters should NOT dedup" in {
def mkfir(defnames: (String, String), params: (String, String)) =
s"""circuit Top :
@@ -253,12 +260,188 @@ class DedupModuleTests extends HighTransformSpec {
| inst a2 of A_
| module A :
| output x: UInt<1>
+ | inst b of B
+ | x <= b.x
+ | module A_ :
+ | output x: UInt<1>
+ | inst b of B_
+ | x <= b.x
+ | module B :
+ | output x: UInt<1>
+ | x <= UInt(1)
+ | module B_ :
+ | output x: UInt<1>
+ | x <= UInt(1)
+ """.stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A
+ | module A :
+ | output x: UInt<1>
+ | inst b of B
+ | x <= b.x
+ | module B :
+ | output x: UInt<1>
+ | x <= UInt(1)
+ """.stripMargin
+ execute(input, check, Seq.empty)
+ }
+
+ "The module A and A_" should "be deduped with fields that sort of match" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A_
+ | module A :
+ | output x: UInt<1>
+ | wire b: {c: UInt<1>}
+ | x <= b.c
+ | module A_ :
+ | output x: UInt<1>
+ | wire b: {b: UInt<1>}
+ | x <= b.b
+ """.stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A
+ | module A :
+ | output x: UInt<1>
+ | wire b: {c: UInt<1>}
+ | x <= b.c
+ """.stripMargin
+ execute(input, check, Seq.empty)
+ }
+
+ "The module A and A_" should "not be deduped with different annotation targets" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A_
+ | module A :
+ | output x: UInt<1>
+ | wire b: UInt<1>
+ | x <= b
+ | module A_ :
+ | output x: UInt<1>
+ | wire b: UInt<1>
+ | x <= b
+ """.stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A_
+ | module A :
+ | output x: UInt<1>
+ | wire b: UInt<1>
+ | x <= b
+ | module A_ :
+ | output x: UInt<1>
+ | wire b: UInt<1>
+ | x <= b
+ """.stripMargin
+ execute(input, check, Seq(dontTouch("A.b")))
+ }
+
+ "The module A and A_" should "be deduped with same annotation targets" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A_
+ | module A :
+ | output x: UInt<1>
+ | wire b: UInt<1>
+ | x <= b
+ | module A_ :
+ | output x: UInt<1>
+ | wire b: UInt<1>
+ | x <= b
+ """.stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A
+ | module A :
+ | output x: UInt<1>
+ | wire b: UInt<1>
+ | x <= b
+ """.stripMargin
+ execute(input, check, Seq(dontTouch("A.b"), dontTouch("A_.b")))
+ }
+ "The module A and A_" should "not be deduped with same annotations with same multi-targets, but which have different root modules" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A_
+ | module A :
+ | output x: UInt<1>
+ | inst b of B
+ | x <= b.x
+ | module A_ :
+ | output x: UInt<1>
| inst b of B_
| x <= b.x
+ | module B :
+ | output x: UInt<1>
+ | x <= UInt(1)
+ | module B_ :
+ | output x: UInt<1>
+ | x <= UInt(1)
+ """.stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A_
+ | module A :
+ | output x: UInt<1>
+ | inst b of B
+ | x <= b.x
| module A_ :
| output x: UInt<1>
+ | inst b of B_
+ | x <= b.x
+ | module B :
+ | output x: UInt<1>
+ | x <= UInt(1)
+ | module B_ :
+ | output x: UInt<1>
+ | x <= UInt(1)
+ """.stripMargin
+ val Top = CircuitTarget("Top")
+ val A = Top.module("A")
+ val B = Top.module("B")
+ val A_ = Top.module("A_")
+ val B_ = Top.module("B_")
+ val annoAB = MultiTargetDummyAnnotation(Seq(A, B), 0)
+ val annoA_B_ = MultiTargetDummyAnnotation(Seq(A_, B_), 0)
+ val cs = execute(input, check, Seq(annoAB, annoA_B_))
+ cs.annotations.toSeq should contain (annoAB)
+ cs.annotations.toSeq should contain (annoA_B_)
+ }
+ "The module A and A_" should "be deduped with same annotations with same multi-targets, that share roots" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A_
+ | module A :
+ | output x: UInt<1>
| inst b of B
| x <= b.x
+ | module A_ :
+ | output x: UInt<1>
+ | inst b of B_
+ | x <= b.x
| module B :
| output x: UInt<1>
| x <= UInt(1)
@@ -279,7 +462,47 @@ class DedupModuleTests extends HighTransformSpec {
| output x: UInt<1>
| x <= UInt(1)
""".stripMargin
- execute(input, check, Seq.empty)
+ val Top = CircuitTarget("Top")
+ val A = Top.module("A")
+ val A_ = Top.module("A_")
+ val annoA = MultiTargetDummyAnnotation(Seq(A, A.instOf("b", "B")), 0)
+ val annoA_ = MultiTargetDummyAnnotation(Seq(A_, A_.instOf("b", "B_")), 0)
+ val cs = execute(input, check, Seq(annoA, annoA_))
+ cs.annotations.toSeq should contain (annoA)
+ cs.annotations.toSeq should not contain (annoA_)
+ cs.deletedAnnotations.isEmpty should be (true)
+ }
+ "The deduping module A and A_" should "renamed internal signals that have different names" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A_
+ | module A :
+ | output y: UInt<1>
+ | y <= UInt(1)
+ | module A_ :
+ | output x: UInt<1>
+ | x <= UInt(1)
+ """.stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | inst a1 of A
+ | inst a2 of A
+ | module A :
+ | output y: UInt<1>
+ | y <= UInt<1>("h1")
+ """.stripMargin
+ val Top = CircuitTarget("Top")
+ val A = Top.module("A")
+ val A_ = Top.module("A_")
+ val annoA = SingleTargetDummyAnnotation(A.ref("y"))
+ val annoA_ = SingleTargetDummyAnnotation(A_.ref("x"))
+ val cs = execute(input, check, Seq(annoA, annoA_))
+ cs.annotations.toSeq should contain (annoA)
+ cs.annotations.toSeq should not contain (SingleTargetDummyAnnotation(A.ref("x")))
+ cs.deletedAnnotations.isEmpty should be (true)
}
}
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