diff options
Diffstat (limited to 'src/test/scala/firrtlTests/formal')
4 files changed, 29 insertions, 29 deletions
diff --git a/src/test/scala/firrtlTests/formal/AssertSubmoduleAssumptionsSpec.scala b/src/test/scala/firrtlTests/formal/AssertSubmoduleAssumptionsSpec.scala index edfd31d3..e413a70d 100644 --- a/src/test/scala/firrtlTests/formal/AssertSubmoduleAssumptionsSpec.scala +++ b/src/test/scala/firrtlTests/formal/AssertSubmoduleAssumptionsSpec.scala @@ -1,4 +1,3 @@ - package firrtlTests.formal import firrtl.{CircuitState, Parser, Transform, UnknownForm} @@ -7,24 +6,25 @@ import firrtl.transforms.formal.AssertSubmoduleAssumptions import firrtl.stage.{Forms, TransformManager} class AssertSubmoduleAssumptionsSpec extends FirrtlFlatSpec { - behavior of "AssertSubmoduleAssumptions" + behavior.of("AssertSubmoduleAssumptions") - val transforms = new TransformManager(Forms.HighForm, Forms.MinimalHighForm) - .flattenedTransformOrder ++ Seq(new AssertSubmoduleAssumptions) + val transforms = new TransformManager(Forms.HighForm, Forms.MinimalHighForm).flattenedTransformOrder ++ Seq( + new AssertSubmoduleAssumptions + ) def run(input: String, check: Seq[String], debug: Boolean = false): Unit = { val circuit = Parser.parse(input.split("\n").toIterator) - val result = transforms.foldLeft(CircuitState(circuit, UnknownForm)) { - (c: CircuitState, p: Transform) => p.runTransform(c) + val result = transforms.foldLeft(CircuitState(circuit, UnknownForm)) { (c: CircuitState, p: Transform) => + p.runTransform(c) } - val lines = result.circuit.serialize.split("\n") map normalized + val lines = result.circuit.serialize.split("\n").map(normalized) if (debug) { println(lines.mkString("\n")) } for (ch <- check) { - lines should contain (ch) + lines should contain(ch) } } diff --git a/src/test/scala/firrtlTests/formal/ConvertAssertsSpec.scala b/src/test/scala/firrtlTests/formal/ConvertAssertsSpec.scala index c70a3ce4..847c211e 100644 --- a/src/test/scala/firrtlTests/formal/ConvertAssertsSpec.scala +++ b/src/test/scala/firrtlTests/formal/ConvertAssertsSpec.scala @@ -8,15 +8,15 @@ import firrtl.transforms.formal.ConvertAsserts class ConvertAssertsSpec extends FirrtlFlatSpec { val preamble = - """circuit DUT: - | module DUT: - | input clock: Clock - | input reset: UInt<1> - | input x: UInt<8> - | output y: UInt<8> - | y <= x - | node ne5 = neq(x, UInt(5)) - |""".stripMargin + """circuit DUT: + | module DUT: + | input clock: Clock + | input reset: UInt<1> + | input x: UInt<8> + | output y: UInt<8> + | y <= x + | node ne5 = neq(x, UInt(5)) + |""".stripMargin "assert nodes" should "be converted to predicated prints and stops" in { val input = preamble + @@ -29,7 +29,7 @@ class ConvertAssertsSpec extends FirrtlFlatSpec { |""".stripMargin val outputCS = ConvertAsserts.execute(CircuitState(parse(input), Nil)) - (parse(outputCS.circuit.serialize)) should be (parse(ref)) + (parse(outputCS.circuit.serialize)) should be(parse(ref)) } "assert nodes with no message" should "omit printed messages" in { @@ -42,6 +42,6 @@ class ConvertAssertsSpec extends FirrtlFlatSpec { |""".stripMargin val outputCS = ConvertAsserts.execute(CircuitState(parse(input), Nil)) - (parse(outputCS.circuit.serialize)) should be (parse(ref)) + (parse(outputCS.circuit.serialize)) should be(parse(ref)) } } diff --git a/src/test/scala/firrtlTests/formal/RemoveVerificationStatementsSpec.scala b/src/test/scala/firrtlTests/formal/RemoveVerificationStatementsSpec.scala index 10e63ae4..40d810c5 100644 --- a/src/test/scala/firrtlTests/formal/RemoveVerificationStatementsSpec.scala +++ b/src/test/scala/firrtlTests/formal/RemoveVerificationStatementsSpec.scala @@ -1,4 +1,3 @@ - package firrtlTests.formal import firrtl.{CircuitState, Parser, Transform, UnknownForm} @@ -7,17 +6,18 @@ import firrtl.testutils.FirrtlFlatSpec import firrtl.transforms.formal.RemoveVerificationStatements class RemoveVerificationStatementsSpec extends FirrtlFlatSpec { - behavior of "RemoveVerificationStatements" + behavior.of("RemoveVerificationStatements") - val transforms = new TransformManager(Forms.HighForm, Forms.MinimalHighForm) - .flattenedTransformOrder ++ Seq(new RemoveVerificationStatements) + val transforms = new TransformManager(Forms.HighForm, Forms.MinimalHighForm).flattenedTransformOrder ++ Seq( + new RemoveVerificationStatements + ) def run(input: String, antiCheck: Seq[String], debug: Boolean = false): Unit = { val circuit = Parser.parse(input.split("\n").toIterator) - val result = transforms.foldLeft(CircuitState(circuit, UnknownForm)) { - (c: CircuitState, p: Transform) => p.runTransform(c) + val result = transforms.foldLeft(CircuitState(circuit, UnknownForm)) { (c: CircuitState, p: Transform) => + p.runTransform(c) } - val lines = result.circuit.serialize.split("\n") map normalized + val lines = result.circuit.serialize.split("\n").map(normalized) if (debug) { println(lines.mkString("\n")) diff --git a/src/test/scala/firrtlTests/formal/VerificationSpec.scala b/src/test/scala/firrtlTests/formal/VerificationSpec.scala index 73d1404d..a8e28c13 100644 --- a/src/test/scala/firrtlTests/formal/VerificationSpec.scala +++ b/src/test/scala/firrtlTests/formal/VerificationSpec.scala @@ -2,14 +2,14 @@ package firrtlTests.formal -import firrtl.{CircuitState, SystemVerilogCompiler, ir} +import firrtl.{ir, CircuitState, SystemVerilogCompiler} import firrtl.testutils.FirrtlFlatSpec import logger.{LogLevel, Logger} import firrtl.options.Dependency import firrtl.stage.TransformManager class VerificationSpec extends FirrtlFlatSpec { - behavior of "Formal" + behavior.of("Formal") it should "generate SystemVerilog verification statements" in { val compiler = new SystemVerilogCompiler @@ -56,7 +56,7 @@ class VerificationSpec extends FirrtlFlatSpec { | end | end |endmodule - |""".stripMargin.split("\n") map normalized + |""".stripMargin.split("\n").map(normalized) executeTest(input, expected, compiler) } |