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-rw-r--r--src/test/scala/firrtlTests/execution/VerilogExecution.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
index 89f27609..913cfc71 100644
--- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala
+++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala
@@ -30,7 +30,7 @@ trait VerilogExecution extends TestExecution {
// Make and run Verilog simulation
verilogToCpp(c.main, testDir, Nil, harness) #&&
- cppToExe(c.main, testDir) ! loggingProcessLogger
+ cppToExe(c.main, testDir) ! loggingProcessLogger
assert(executeExpectingSuccess(c.main, testDir))
}
}