1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index eb955f29..eb3d1a96 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -15,7 +15,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       ZeroWidth)
   private def exec (input: String) = {
@@ -218,12 +218,12 @@ class ZeroWidthVerilog extends FirrtlFlatSpec {
   "Circuit" should "accept zero width wires" in {
     val compiler = new VerilogCompiler
     val input =
-      """circuit Top : 
-         |  module Top : 
+      """circuit Top :
+         |  module Top :
          |    input y: UInt<0>
          |    output x: UInt<3>
          |    x <= y""".stripMargin
-    val check = 
+    val check =
       """module Top(
         |  output  [2:0] x
         |);