1 files changed, 17 insertions, 4 deletions
diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index 90926bc1..8c39dc1e 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -11,7 +11,7 @@ import firrtl.Parser
 import firrtl.passes._
 
 class ZeroWidthTests extends FirrtlFlatSpec {
-  val passes = Seq(
+  val transforms = Seq(
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
@@ -19,9 +19,10 @@ class ZeroWidthTests extends FirrtlFlatSpec {
       InferWidths,
       ZeroWidth)
   private def exec (input: String) = {
-    passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }.serialize
+    val circuit = parse(input)
+    transforms.foldLeft(CircuitState(circuit, UnknownForm)) {
+      (c: CircuitState, p: Transform) => p.runTransform(c)
+    }.circuit.serialize
   }
    // =============================
   "Zero width port" should " be deleted" in {
@@ -105,6 +106,18 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    skip""".stripMargin
       (parse(exec(input)).serialize) should be (parse(check).serialize)
   }
+  "IsInvalid on <0>" should "be deleted" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    output y: UInt<0>
+        |    y is invalid""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    skip""".stripMargin
+      (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
   "Expression in node with type <0>" should "be replaced by UInt<1>(0)" in {
     val input =
       """circuit Top :