1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index 6da73157..4f8fd9fe 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -705,7 +705,7 @@ class WiringTests extends FirrtlFlatSpec {
       (c: Circuit, p: Pass) => p.run(c)
     }
     val wiringXForm = new WiringTransform()
-    val retC = wiringXForm.execute(CircuitState(c, MidForm, Some(AnnotationMap(Seq(source, sink))), None)).circuit
+    val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit
     (parse(retC.serialize).serialize) should be (parse(check).serialize)
   }
 
@@ -743,7 +743,7 @@ class WiringTests extends FirrtlFlatSpec {
       (c: Circuit, p: Pass) => p.run(c)
     }
     val wiringXForm = new WiringTransform()
-    val retC = wiringXForm.execute(CircuitState(c, MidForm, Some(AnnotationMap(Seq(source, sink))), None)).circuit
+    val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit
     (parse(retC.serialize).serialize) should be (parse(check).serialize)
   }
 
@@ -789,7 +789,7 @@ class WiringTests extends FirrtlFlatSpec {
       (c: Circuit, p: Pass) => p.run(c)
     }
     val wiringXForm = new WiringTransform()
-    val retC = wiringXForm.execute(CircuitState(c, MidForm, Some(AnnotationMap(Seq(source, sink))), None)).circuit
+    val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit
     (parse(retC.serialize).serialize) should be (parse(check).serialize)
   }