1 files changed, 42 insertions, 36 deletions
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 770c2785..d1d02ee2 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -22,42 +22,6 @@ class WidthSpec extends FirrtlFlatSpec {
     }
   }
 
-  "Add of UInt<2> and SInt<2>" should "return SInt<4>" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes,
-      InferWidths)
-    val input =
-      """circuit Unit :
-        |  module Unit :
-        |    input x: UInt<2>
-        |    input y: SInt<2>
-        |    output z: SInt
-        |    z <= add(x, y)""".stripMargin
-    val check = Seq( "output z : SInt<4>")
-    executeTest(input, check, passes)
-  }
-  "SInt<2> - UInt<3>" should "return SInt<5>" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes,
-      InferWidths)
-    val input =
-      """circuit Unit :
-        |  module Unit :
-        |    input x: UInt<3>
-        |    input y: SInt<2>
-        |    output z: SInt
-        |    z <= sub(y, x)""".stripMargin
-    val check = Seq( "output z : SInt<5>")
-    executeTest(input, check, passes)
-  }
   "Dshl by 20 bits" should "result in an error" in {
     val passes = Seq(
       ToWorkingIR,
@@ -121,4 +85,46 @@ class WidthSpec extends FirrtlFlatSpec {
       executeTest(input, Nil, passes)
     }
   }
+
+  "Add of UInt<2> and SInt<2>" should "error" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      InferWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input x: UInt<2>
+        |    input y: SInt<2>
+        |    output z: SInt
+        |    z <= add(x, y)""".stripMargin
+    val check = Seq( "output z : SInt<4>")
+    intercept[PassExceptions] {
+      executeTest(input, check, passes)
+    }
+  }
+
+  "SInt<2> - UInt<3>" should "error" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      InferWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input x: UInt<3>
+        |    input y: SInt<2>
+        |    output z: SInt
+        |    z <= sub(y, x)""".stripMargin
+    val check = Seq( "output z : SInt<5>")
+    intercept[PassExceptions] {
+      executeTest(input, check, passes)
+    }
+  }
 }