1 files changed, 10 insertions, 10 deletions
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 058cc1fa..96bd249c 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -11,10 +11,10 @@ import firrtl.passes._
 import firrtl.Parser.IgnoreInfo
 
 class WidthSpec extends FirrtlFlatSpec {
-  private def executeTest(input: String, expected: Seq[String], passes: Seq[Pass]) = {
-    val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+  private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = {
+    val c = passes.foldLeft(CircuitState(Parser.parse(input.split("\n").toIterator), UnknownForm)) {
+      (c: CircuitState, p: Transform) => p.runTransform(c)
+    }.circuit
     val lines = c.serialize.split("\n") map normalized
 
     expected foreach { e =>
@@ -54,7 +54,7 @@ class WidthSpec extends FirrtlFlatSpec {
       InferTypes,
       CheckTypes,
       ResolveGenders,
-      InferWidths,
+      new InferWidths,
       CheckWidths)
     val input =
       """circuit Unit :
@@ -77,7 +77,7 @@ class WidthSpec extends FirrtlFlatSpec {
       InferTypes,
       CheckTypes,
       ResolveGenders,
-      InferWidths,
+      new InferWidths,
       CheckWidths)
     val input =
      s"""circuit Unit :
@@ -96,7 +96,7 @@ class WidthSpec extends FirrtlFlatSpec {
       InferTypes,
       CheckTypes,
       ResolveGenders,
-      InferWidths,
+      new InferWidths,
       CheckWidths)
     val input =
       """circuit Unit :
@@ -121,7 +121,7 @@ class WidthSpec extends FirrtlFlatSpec {
       InferTypes,
       CheckTypes,
       ResolveGenders,
-      InferWidths)
+      new InferWidths)
     val input =
       """circuit Unit :
         |  module Unit :
@@ -143,7 +143,7 @@ class WidthSpec extends FirrtlFlatSpec {
       InferTypes,
       CheckTypes,
       ResolveGenders,
-      InferWidths)
+      new InferWidths)
     val input =
       """circuit Unit :
         |  module Unit :
@@ -166,7 +166,7 @@ class WidthSpec extends FirrtlFlatSpec {
       InferTypes,
       CheckTypes,
       ResolveGenders,
-      InferWidths,
+      new InferWidths,
       CheckWidths)
     val input =
       """|circuit Foo :