diff options
Diffstat (limited to 'src/test/scala/firrtlTests/VerilogMemDelaySpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogMemDelaySpec.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala b/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala index e7f27d0e..52f9ee36 100644 --- a/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala +++ b/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala @@ -5,9 +5,10 @@ package firrtlTests import firrtl._ import firrtl.passes.memlib.VerilogMemDelays import firrtl.passes.CheckHighForm -import org.scalatest.{FreeSpec, Matchers} +import org.scalatest.freespec.AnyFreeSpec +import org.scalatest.matchers.should.Matchers -class VerilogMemDelaySpec extends FreeSpec with Matchers { +class VerilogMemDelaySpec extends AnyFreeSpec with Matchers { "The following low FIRRTL should be parsed by VerilogMemDelays" in { val input = """ |