diff options
Diffstat (limited to 'src/test/scala/firrtlTests/VerilogEmitterTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogEmitterTests.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 1f6142bc..e9bf5429 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -37,10 +37,9 @@ import firrtl.passes._ import firrtl.Parser.IgnoreInfo class DoPrimVerilog extends FirrtlFlatSpec { - def parse (input:String) = Parser.parse(input.split("\n").toIterator, IgnoreInfo) private def executeTest(input: String, expected: Seq[String], compiler: Compiler) = { val writer = new StringWriter() - compiler.compile(parse(input), new AnnotationMap(Seq.empty), writer) + compiler.compile(CircuitState(parse(input), ChirrtlForm), writer) val lines = writer.toString().split("\n") map normalized expected foreach { e => lines should contain(e) |