1 files changed, 19 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 6928718a..40b66917 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -130,4 +130,23 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
       """.stripMargin
     compiler.compile(CircuitState(parse(input), ChirrtlForm), new java.io.StringWriter)
   }
+  "AsClock" should "emit correctly" in {
+    val compiler = new VerilogCompiler
+    val input =
+      """circuit Test :
+        |  module Test :
+        |    input in : UInt<1>
+        |    output out : Clock
+        |    out <= asClock(in)
+        |""".stripMargin
+    val check =
+      """module Test(
+        |  input   in,
+        |  output  out
+        |);
+        |  assign out = in;
+        |endmodule
+        |""".stripMargin.split("\n") map normalized
+    executeTest(input, check, compiler)
+  }
 }