diff options
Diffstat (limited to 'src/test/scala/firrtlTests/VerilogEmitterTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/VerilogEmitterTests.scala | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index c5d0eacc..825d706f 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -13,12 +13,12 @@ class DoPrimVerilog extends FirrtlFlatSpec { "Xorr" should "emit correctly" in { val compiler = new VerilogCompiler val input = - """circuit Xorr : - | module Xorr : + """circuit Xorr : + | module Xorr : | input a: UInt<4> | output b: UInt<1> | b <= xorr(a)""".stripMargin - val check = + val check = """module Xorr( | input [3:0] a, | output b @@ -31,12 +31,12 @@ class DoPrimVerilog extends FirrtlFlatSpec { "Andr" should "emit correctly" in { val compiler = new VerilogCompiler val input = - """circuit Andr : - | module Andr : + """circuit Andr : + | module Andr : | input a: UInt<4> | output b: UInt<1> | b <= andr(a)""".stripMargin - val check = + val check = """module Andr( | input [3:0] a, | output b @@ -49,12 +49,12 @@ class DoPrimVerilog extends FirrtlFlatSpec { "Orr" should "emit correctly" in { val compiler = new VerilogCompiler val input = - """circuit Orr : - | module Orr : + """circuit Orr : + | module Orr : | input a: UInt<4> | output b: UInt<1> | b <= orr(a)""".stripMargin - val check = + val check = """module Orr( | input [3:0] a, | output b @@ -187,8 +187,8 @@ class DoPrimVerilog extends FirrtlFlatSpec { |""".stripMargin val check = """module Test( - | input [7:0] in, - | output out + | input [7:0] in, + | output out |); | wire [7:0] _GEN_0; | assign out = _GEN_0[0]; |