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Diffstat (limited to 'src/test/scala/firrtlTests/UnitTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index 018a35f6..a38a8def 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -24,7 +24,7 @@ class UnitTests extends FirrtlFlatSpec { val c = transforms.foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, t: Transform) => t.runTransform(c) }.circuit - CircuitState(c, UnknownForm, None, None) + CircuitState(c, UnknownForm, Seq(), None) } "Pull muxes" should "not be exponential in runtime" in { |