1 files changed, 17 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index e2f8f729..cb07448f 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -304,4 +304,21 @@ class UnitTests extends FirrtlFlatSpec {
     }
 
   }
+
+  "Conditional conection of clocks" should "throw an exception" in {
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input clock1 : Clock
+        |    input clock2 : Clock
+        |    input sel : UInt<1>
+        |    output clock3 : Clock
+        |    clock3 <= clock1
+        |    when sel :
+        |      clock3 <= clock2
+        |""".stripMargin
+    intercept[PassExceptions] { // Both MuxClock and InvalidConnect are thrown
+      compileToVerilog(input)
+    }
+  }
 }