1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 44799829..018a35f6 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -313,7 +313,7 @@ class UnitTests extends FirrtlFlatSpec {
     }
   }
 
-  "Conditional conection of clocks" should "throw an exception" in {
+  "Conditional connection of clocks" should "throw an exception" in {
     val input =
       """circuit Unit :
         |  module Unit :
@@ -325,7 +325,7 @@ class UnitTests extends FirrtlFlatSpec {
         |    when sel :
         |      clock3 <= clock2
         |""".stripMargin
-    intercept[PassExceptions] { // Both MuxClock and InvalidConnect are thrown
+    intercept[EmitterException] {
       compileToVerilog(input)
     }
   }