diff options
Diffstat (limited to 'src/test/scala/firrtlTests/UnitTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index 8f128274..a864bfe5 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -110,18 +110,8 @@ class UnitTests extends FirrtlFlatSpec { | out <= bits(mux(a, b, c), 0, 0) |""".stripMargin - "Emitting a nested expression" should "throw an exception" in { + "Emitting a nested expression" should "compile" in { val passes = Seq(ToWorkingIR, InferTypes, ResolveKinds) - intercept[PassException] { - val c = Parser.parse(splitExpTestCode.split("\n").toIterator) - val c2 = passes.foldLeft(c)((c, p) => p.run(c)) - val writer = new StringWriter() - (new VerilogEmitter).emit(CircuitState(c2, LowForm), writer) - } - } - - "After splitting, emitting a nested expression" should "compile" in { - val passes = Seq(ToWorkingIR, SplitExpressions, InferTypes) val c = Parser.parse(splitExpTestCode.split("\n").toIterator) val c2 = passes.foldLeft(c)((c, p) => p.run(c)) val writer = new StringWriter() |