1 files changed, 6 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index 8367f152..25f845bc 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -5,6 +5,7 @@ package firrtlTests
 import firrtl._
 import firrtl.ir._
 import firrtl.passes._
+import firrtl.transforms._
 import firrtl.passes.memlib._
 import annotations._
 
@@ -21,7 +22,7 @@ class ReplSeqMemSpec extends SimpleTransformSpec {
     new SeqTransform {
       def inputForm = LowForm
       def outputForm = LowForm
-      def transforms = Seq(ConstProp, CommonSubexpressionElimination, DeadCodeElimination, RemoveEmpty)
+      def transforms = Seq(ConstProp, CommonSubexpressionElimination, new DeadCodeElimination, RemoveEmpty)
     }
   )
 
@@ -199,7 +200,7 @@ circuit CustomMemory :
     smem mem_1 : UInt<16>[7]
     read mport _T_17 = mem_0[io.rAddr], clock
     read mport _T_19 = mem_1[io.rAddr], clock
-    io.dO <= _T_17
+    io.dO <= and(_T_17, _T_19)
     when io.wEn :
       write mport _T_18 = mem_0[io.wAddr], clock
       write mport _T_20 = mem_1[io.wAddr], clock
@@ -218,7 +219,7 @@ circuit CustomMemory :
       case e: ExtModule =>  true
       case _ => false
     }
-    require(numExtMods == 2)
+    numExtMods should be (2)
     (new java.io.File(confLoc)).delete()
   }
 
@@ -237,7 +238,7 @@ circuit CustomMemory :
     read mport _T_17 = mem_0[io.rAddr], clock
     read mport _T_19 = mem_1[io.rAddr], clock
     read mport _T_21 = mem_2[io.rAddr], clock
-    io.dO <= _T_17
+    io.dO <= and(_T_17, and(_T_19, _T_21))
     when io.wEn :
       write mport _T_18 = mem_0[io.wAddr], clock
       write mport _T_20 = mem_1[io.wAddr], clock
@@ -258,7 +259,7 @@ circuit CustomMemory :
       case e: ExtModule =>  true
       case _ => false
     }
-    require(numExtMods == 2)
+    numExtMods should be (2)
     (new java.io.File(confLoc)).delete()
   }