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Diffstat (limited to 'src/test/scala/firrtlTests/ReplSeqMemTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/ReplSeqMemTests.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala index 0831bb31..8367f152 100644 --- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala +++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala @@ -65,6 +65,7 @@ circuit Top : val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:Top:-o:"+confLoc))) val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(aMap))) // Check correctness of firrtl + println(res.annotations) parse(res.getEmittedCircuit.value) (new java.io.File(confLoc)).delete() } |