1 files changed, 17 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
index d15e6908..e40a770b 100644
--- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala
+++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
@@ -165,4 +165,21 @@ class RemoveWiresSpec extends FirrtlFlatSpec {
     // Check declaration before use is maintained
     passes.CheckHighForm.execute(result)
   }
+
+  it should "order registers with async reset correctly" in {
+    val result = compileBody(s"""
+      |input clock : Clock
+      |input reset : UInt<1>
+      |input in : UInt<8>
+      |output out : UInt<8>
+      |wire areset : AsyncReset
+      |reg r : UInt<8>, clock with : (reset => (areset, UInt(0)))
+      |areset <= asAsyncReset(reset)
+      |r <= in
+      |out <= r
+      |""".stripMargin
+    )
+    // Check declaration before use is maintained
+    passes.CheckHighForm.execute(result)
+  }
 }