diff options
Diffstat (limited to 'src/test/scala/firrtlTests/LoweringCompilersSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index bdc72e7b..d56ca657 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -247,7 +247,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers { new firrtl.transforms.ReplaceTruncatingArithmetic, new firrtl.transforms.InlineBitExtractionsTransform, new firrtl.transforms.PropagatePresetAnnotations, - new firrtl.transforms.InlineCastsTransform, + new firrtl.transforms.InlineAcrossCastsTransform, new firrtl.transforms.LegalizeClocksTransform, new firrtl.transforms.FlattenRegUpdate, firrtl.passes.VerilogModulusCleanup, @@ -271,7 +271,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers { new firrtl.transforms.ReplaceTruncatingArithmetic, new firrtl.transforms.InlineBitExtractionsTransform, new firrtl.transforms.PropagatePresetAnnotations, - new firrtl.transforms.InlineCastsTransform, + new firrtl.transforms.InlineAcrossCastsTransform, new firrtl.transforms.LegalizeClocksTransform, new firrtl.transforms.FlattenRegUpdate, new firrtl.transforms.DeadCodeElimination, |