diff options
Diffstat (limited to 'src/test/scala/firrtlTests/InfoSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/InfoSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala index 4cb25640..8d49d753 100644 --- a/src/test/scala/firrtlTests/InfoSpec.scala +++ b/src/test/scala/firrtlTests/InfoSpec.scala @@ -59,8 +59,8 @@ class InfoSpec extends FirrtlFlatSpec { ) result should containTree { case DefRegister(Info1, "r", _,_,_,_) => true } result should containLine (s"reg [7:0] r; //$Info1") - result should containTree { case DefWire(Info2, "w", _) => true } - result should containLine (s"wire [7:0] w; //$Info2") + result should containTree { case DefNode(Info2, "w", _) => true } + result should containLine (s"wire [7:0] w; //$Info2") // Node "w" declaration in Verilog result should containTree { case DefNode(Info3, "n", _) => true } result should containLine (s"wire [7:0] n; //$Info3") result should containLine (s"assign n = w | x; //$Info3") |