diff options
Diffstat (limited to 'src/test/scala/firrtlTests/InferReadWriteSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/InferReadWriteSpec.scala | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala index 82c9d65f..34e228be 100644 --- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala +++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala @@ -71,8 +71,8 @@ circuit sram6t : T_5 <= io.wdata """.stripMargin - val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t"))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + val annos = Seq(memlib.InferReadWriteAnnotation) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) } @@ -102,8 +102,8 @@ circuit sram6t : io.dataOut <= _T_22 """.stripMargin - val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t"))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + val annos = Seq(memlib.InferReadWriteAnnotation) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) } @@ -133,9 +133,9 @@ circuit sram6t : T_5 <= io.wdata """.stripMargin - val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t"))) + val annos = Seq(memlib.InferReadWriteAnnotation) intercept[InferReadWriteCheckException] { - compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) } } } |