1 files changed, 4 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
index a5eea147..91dc911c 100644
--- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala
+++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
@@ -42,6 +42,7 @@ class InferReadWriteSpec extends SimpleTransformSpec {
     def passSeq = Seq(InferReadWriteCheckPass)
   }
 
+  def emitter = new MiddleFirrtlEmitter
   def transforms = Seq(
     new ChirrtlToHighFirrtl,
     new IRToWorkingIR,
@@ -76,10 +77,9 @@ circuit sram6t :
 """.stripMargin
 
     val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t")))
-    val writer = new java.io.StringWriter
-    compile(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)), writer)
+    val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)))
     // Check correctness of firrtl
-    parse(writer.toString)
+    parse(res.getEmittedCircuit.value)
   }
 
   "Infer ReadWrite Ports" should "not infer readwrite ports for the difference clocks" in {
@@ -108,9 +108,8 @@ circuit sram6t :
 """.stripMargin
 
     val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t")))
-    val writer = new java.io.StringWriter
     intercept[InferReadWriteCheckException] {
-      compile(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)), writer)
+      compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)))
     }
   }
 }