diff options
Diffstat (limited to 'src/test/scala/firrtlTests/FirrtlSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/FirrtlSpec.scala | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala index f77b47f3..a45af8c7 100644 --- a/src/test/scala/firrtlTests/FirrtlSpec.scala +++ b/src/test/scala/firrtlTests/FirrtlSpec.scala @@ -12,7 +12,8 @@ import scala.io.Source import firrtl._ import firrtl.Parser.IgnoreInfo -import firrtl.annotations +import firrtl.annotations._ +import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation} import firrtl.util.BackendCompilationUtilities trait FirrtlRunners extends BackendCompilationUtilities { @@ -82,6 +83,16 @@ trait FirrtlRunners extends BackendCompilationUtilities { } trait FirrtlMatchers extends Matchers { + def dontTouch(path: String): Annotation = { + val parts = path.split('.') + require(parts.size >= 2, "Must specify both module and component!") + val name = ComponentName(parts.tail.mkString("."), ModuleName(parts.head, CircuitName("Top"))) + DontTouchAnnotation(name) + } + def dontDedup(mod: String): Annotation = { + require(mod.split('.').size == 1, "Can only specify a Module, not a component or instance") + NoDedupAnnotation(ModuleName(mod, CircuitName("Top"))) + } // Replace all whitespace with a single space and remove leading and // trailing whitespace // Note this is intended for single-line strings, no newlines @@ -94,8 +105,13 @@ trait FirrtlMatchers extends Matchers { * compiler will be run on input then emitted result will each be split into * lines and normalized. */ - def executeTest(input: String, expected: Seq[String], compiler: Compiler) = { - val finalState = compiler.compileAndEmit(CircuitState(parse(input), ChirrtlForm)) + def executeTest( + input: String, + expected: Seq[String], + compiler: Compiler, + annotations: Seq[Annotation] = Seq.empty) = { + val annoMap = AnnotationMap(annotations) + val finalState = compiler.compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annoMap))) val lines = finalState.getEmittedCircuit.value split "\n" map normalized for (e <- expected) { lines should contain (e) |
