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Diffstat (limited to 'src/test/scala/firrtlTests/FirrtlSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/FirrtlSpec.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala index 95b09d93..88238785 100644 --- a/src/test/scala/firrtlTests/FirrtlSpec.scala +++ b/src/test/scala/firrtlTests/FirrtlSpec.scala @@ -59,6 +59,9 @@ trait FirrtlRunners extends BackendCompilationUtilities { val compiler = new MinimumVerilogCompiler val prefix = circuit.main val testDir = createTestDirectory(prefix + "_equivalence_test") + val firrtlWriter = new PrintWriter(s"${testDir.getAbsolutePath}/$prefix.fir") + firrtlWriter.write(input) + firrtlWriter.close() val customVerilog = compiler.compileAndEmit(CircuitState(circuit, HighForm, customAnnotations), new GetNamespace +: new RenameTop(s"${prefix}_custom") +: customTransforms) |