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-rw-r--r--src/test/scala/firrtlTests/DCETests.scala5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index ea34d4be..d1848ab8 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -60,9 +60,8 @@ class DCETests extends FirrtlFlatSpec {
| module Top :
| input x : UInt<1>
| output z : UInt<1>
- | wire a : UInt<1>
- | z <= x
- | a <= x""".stripMargin
+ | node a = x
+ | z <= x""".stripMargin
exec(input, check, Seq(dontTouch("Top.a")))
}
"Unread register" should "be deleted" in {