1 files changed, 51 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
new file mode 100644
index 00000000..4a3faf6b
--- /dev/null
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -0,0 +1,51 @@
+// See LICENSE for license details.
+
+package firrtlTests
+
+import firrtl.ir.Circuit
+import firrtl._
+import firrtl.passes.Pass
+import firrtl.ir._
+
+class CustomTransformSpec extends FirrtlFlatSpec {
+  behavior of "Custom Transforms"
+
+  they should "be able to introduce high firrtl" in {
+    // Simple module
+    val delayModuleString = """
+      |circuit Delay :
+      |  module Delay :
+      |    input clk : Clock
+      |    input reset : UInt<1>
+      |    input a : UInt<32>
+      |    input en : UInt<1>
+      |    output b : UInt<32>
+      |
+      |    reg r : UInt<32>, clk
+      |    r <= r
+      |    when en :
+      |      r <= a
+      |    b <= r
+      |""".stripMargin
+    val delayModuleCircuit = parse(delayModuleString)
+    val delayModule = delayModuleCircuit.modules.find(_.name == delayModuleCircuit.main).get
+
+    class ReplaceExtModuleTransform extends PassBasedTransform {
+      class ReplaceExtModule extends Pass {
+        def name = "Replace External Module"
+        def run(c: Circuit): Circuit = c.copy(
+          modules = c.modules map {
+            case ExtModule(_, "Delay", _, _, _) => delayModule
+            case other => other
+          }
+        )
+      }
+      def passSeq = Seq(new ReplaceExtModule)
+      def inputForm = LowForm
+      def outputForm = HighForm
+    }
+
+    runFirrtlTest("CustomTransform", "/features", customTransforms = List(new ReplaceExtModuleTransform))
+  }
+}
+