aboutsummaryrefslogtreecommitdiff
path: root/src/test/scala/firrtlTests/ConstantPropagationTests.scala
diff options
context:
space:
mode:
Diffstat (limited to 'src/test/scala/firrtlTests/ConstantPropagationTests.scala')
-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala39
1 files changed, 31 insertions, 8 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 95785717..c94adbf6 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -2,11 +2,11 @@
package firrtlTests
-import org.scalatest.Matchers
+import firrtl._
import firrtl.ir.Circuit
import firrtl.Parser.IgnoreInfo
-import firrtl.Parser
import firrtl.passes._
+import firrtl.transforms._
// Tests the following cases for constant propagation:
// 1) Unsigned integers are always greater than or
@@ -16,17 +16,17 @@ import firrtl.passes._
// 3) Values are always greater than a number smaller
// than their minimum value
class ConstantPropagationSpec extends FirrtlFlatSpec {
- val passes = Seq(
+ val transforms = Seq(
ToWorkingIR,
ResolveKinds,
InferTypes,
ResolveGenders,
InferWidths,
- ConstProp)
- private def exec (input: String) = {
- passes.foldLeft(parse(input)) {
- (c: Circuit, p: Pass) => p.run(c)
- }.serialize
+ new ConstantPropagation)
+ private def exec(input: String) = {
+ transforms.foldLeft(CircuitState(parse(input), UnknownForm)) {
+ (c: CircuitState, t: Transform) => t.runTransform(c)
+ }.circuit.serialize
}
// =============================
"The rule x >= 0 " should " always be true if x is a UInt" in {
@@ -349,4 +349,27 @@ class ConstantPropagationSpec extends FirrtlFlatSpec {
"""
(parse(exec(input))) should be (parse(check))
}
+
+ // =============================
+ "ConstProp" should "work across wires" in {
+ val input =
+"""circuit Top :
+ module Top :
+ input x : UInt<1>
+ output y : UInt<1>
+ wire z : UInt<1>
+ y <= z
+ z <= mux(x, UInt<1>(0), UInt<1>(0))
+"""
+ val check =
+"""circuit Top :
+ module Top :
+ input x : UInt<1>
+ output y : UInt<1>
+ wire z : UInt<1>
+ y <= UInt<1>(0)
+ z <= UInt<1>(0)
+"""
+ (parse(exec(input))) should be (parse(check))
+ }
}