1 files changed, 32 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index 348ed300..dc70847a 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -13,6 +13,7 @@ import firrtl.{
   Compiler,
   HighFirrtlCompiler,
   MiddleFirrtlCompiler,
+  MinimumVerilogCompiler,
   LowFirrtlCompiler,
   Parser,
   VerilogCompiler
@@ -153,3 +154,34 @@ class VerilogCompilerSpec extends CompilerSpec with Matchers {
       getOutput should be (check)
    }
 }
+
+class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers {
+  val input = """|circuit Top:
+                 |  module Top:
+                 |    output b: UInt<1>[3]
+                 |    node c = bits(UInt<3>("h7"), 2, 2)
+                 |    node d = shr(UInt<3>("h7"), 2)
+                 |    b[0] is invalid
+                 |    b[1] <= c
+                 |    b[2] <= d
+                 |""".stripMargin
+  val check = """|module Top(
+                 |  output  b_0,
+                 |  output  b_1,
+                 |  output  b_2
+                 |);
+                 |  wire  c;
+                 |  wire  d;
+                 |  assign c = 1'h1;
+                 |  assign d = 1'h1;
+                 |  assign b_0 = 1'h0;
+                 |  assign b_1 = c;
+                 |  assign b_2 = d;
+                 |endmodule
+                 |""".stripMargin
+  def compiler = new MinimumVerilogCompiler()
+
+  "A circuit's minimum Verilog output" should "not have constants propagated or dead code eliminated" in {
+    getOutput should be (check)
+  }
+}