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Diffstat (limited to 'src/test/scala/firrtlTests/ChirrtlSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/ChirrtlSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala index dd2b7e31..0059d7ed 100644 --- a/src/test/scala/firrtlTests/ChirrtlSpec.scala +++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala @@ -67,7 +67,7 @@ class ChirrtlSpec extends FirrtlFlatSpec { | infer mport y = ram[UInt(4)], newClock | y <= UInt(5) """.stripMargin - passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) { + passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { (c: Circuit, p: Pass) => p.run(c) } } |