1 files changed, 2 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
index fd984661..c963c8ae 100644
--- a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
@@ -10,7 +10,6 @@ import annotations._
 
 class ChirrtlMemSpec extends LowTransformSpec {
   object MemEnableCheckPass extends Pass {
-    val name = "Check Enable Signal for Chirrtl Mems"
     type Netlist = collection.mutable.HashMap[String, Expression]
     def buildNetlist(netlist: Netlist)(s: Statement): Statement = {
       s match {
@@ -51,10 +50,10 @@ class ChirrtlMemSpec extends LowTransformSpec {
     }
   }
 
-  def transform = new PassBasedTransform {
+  def transform = new SeqTransform {
     def inputForm = LowForm
     def outputForm = LowForm
-    def passSeq = Seq(ConstProp, MemEnableCheckPass)
+    def transforms = Seq(ConstProp, MemEnableCheckPass)
   }
 
   "Sequential Memory" should "have correct enable signals" in {