1 files changed, 2 insertions, 4 deletions
diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala
index 773a0bf3..0d31038a 100644
--- a/src/test/scala/firrtlTests/CInferMDirSpec.scala
+++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala
@@ -10,8 +10,6 @@ import annotations._
 
 class CInferMDir extends LowTransformSpec {
   object CInferMDirCheckPass extends Pass {
-    val name = "Check Enable Signal for Chirrtl Mems"
-
     // finds the memory and check its read port
     def checkStmt(s: Statement): Boolean = s match {
       case s: DefMemory if s.name == "indices" =>
@@ -38,10 +36,10 @@ class CInferMDir extends LowTransformSpec {
     }
   }
 
-  def transform = new PassBasedTransform {
+  def transform = new SeqTransform {
     def inputForm = LowForm
     def outputForm = LowForm
-    def passSeq = Seq(ConstProp, CInferMDirCheckPass)
+    def transforms = Seq(ConstProp, CInferMDirCheckPass)
   }
 
   "Memory" should "have correct mem port directions" in {