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Diffstat (limited to 'src/test/scala/firrtlTests/CInferMDirSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/CInferMDirSpec.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala index 299142d9..a0f55794 100644 --- a/src/test/scala/firrtlTests/CInferMDirSpec.scala +++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala @@ -68,8 +68,7 @@ circuit foo : bar <= io.in """.stripMargin - val annotationMap = AnnotationMap(Nil) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) } |